diff --git a/doc/main.tex b/doc/main.tex
new file mode 100644
index 0000000..e69de29
diff --git a/src/ver/__ b/src/ver/__
new file mode 100644
index 0000000..ac50e70
--- /dev/null
+++ b/src/ver/__
@@ -0,0 +1,2 @@
+yosys -p "synth_ice40 -top SOC -json step2.json" step2.v clockworks.v
+
diff --git a/src/ver/clockworks.v b/src/ver/clockworks.v
new file mode 100644
index 0000000..5c5a675
--- /dev/null
+++ b/src/ver/clockworks.v
@@ -0,0 +1,117 @@
+/*
+ * Clockworks includes
+ *   - gearbox to divide clock frequency, used
+ *     to let you observe how the design behaves
+ *     one cycle at a time.
+ *   - reset mechanism that resets the design
+ *     during the first microseconds because
+ *     reading in Ice40 BRAM during the first 
+ *     few microseconds returns garbage!
+ * 
+ * Parameters
+ *     SLOW number of bits of gearbox. Clock divider
+ *       is (1 << SLOW)
+ * 
+ * Macros
+ *     NEGATIVE_RESET if board's RESET pin goes low on reset
+ *     ICE_STICK if board is an IceStick.
+ */    
+
+`ifdef ECP5_EVN
+`define NEGATIVE_RESET
+`endif
+
+`ifdef ARTY
+`define NEGATIVE_RESET
+`endif
+
+module Clockworks 
+(
+   input  CLK, // clock pin of the board
+   input  RESET, // reset pin of the board
+   output clk,   // (optionally divided) clock for the design.
+                 // divided if SLOW is different from zero.
+   output resetn // (optionally timed) negative reset for the design
+);               
+   parameter SLOW=0;
+
+   generate
+
+/****************************************************
+
+ Slow speed mode.
+ - Create a clock divider to let observe what happens.
+ - Nothing special to do for reset
+ 
+ ****************************************************/
+      if(SLOW != 0) begin
+	 // Factor is 1 << slow_bit.
+	 // Since simulation is approx. 16 times slower than
+	 // actual device we use different factor for bosh.
+`ifdef BENCH
+   localparam slow_bit=SLOW-4;
+`else
+   localparam slow_bit=SLOW;
+`endif
+	 reg [slow_bit:0] slow_CLK = 0;
+	 always @(posedge CLK) begin
+	    slow_CLK <= slow_CLK + 1;
+	 end
+	 assign clk = slow_CLK[slow_bit];
+
+`ifdef NEGATIVE_RESET
+	 assign resetn = RESET;
+`else
+	 assign resetn = !RESET;
+`endif
+
+
+/****************************************************
+
+ High speed mode.
+ - Nothing special to do for the clock
+ - A timer that resets the design during the first
+   few microseconds, because reading in Ice40 BRAM 
+   during the first few microseconds returns garbage!
+ 
+ ****************************************************/
+	 
+      end else begin 
+	
+        // Assign clock directly without PLL
+        assign clk = CLK;
+
+// Preserve resources on Ice40HX1K (IceStick) with 
+// carefully tuned counter (12 bits suffice). 
+// For other FPGAs, use larger counter.
+`ifdef ICE_STICK
+	 reg [11:0] 	    reset_cnt = 0;
+`else   
+	 reg [15:0] 	    reset_cnt = 0;
+`endif   
+	 assign resetn = &reset_cnt;
+
+`ifdef NEGATIVE_RESET
+	 always @(posedge clk,negedge RESET) begin
+	    if(!RESET) begin
+	       reset_cnt <= 0;
+	    end else begin
+	       reset_cnt <= reset_cnt + !resetn;
+	    end
+	 end
+`else   
+	 always @(posedge clk,posedge RESET) begin
+	    if(RESET) begin
+	       reset_cnt <= 0;
+	    end else begin
+	       /* verilator lint_off WIDTH */
+	       reset_cnt <= reset_cnt + !resetn;
+	       /* verilator lint_on WIDTH */	       
+	    end
+	 end
+`endif   
+      end
+   endgenerate
+
+endmodule
+
diff --git a/src/ver/soc.pcf b/src/ver/soc.pcf
new file mode 100644
index 0000000..b487cd1
--- /dev/null
+++ b/src/ver/soc.pcf
@@ -0,0 +1,10 @@
+set_io CLK   35      # wejście zegarowe
+set_io RESET 37      # przycisk reset
+set_io RXD   44      # UART RX
+set_io TXD   43      # UART TX
+set_io LEDS[0] 11    # diody LED
+set_io LEDS[1] 13
+set_io LEDS[2] 14
+set_io LEDS[3] 15
+set_io LEDS[4] 16
+
diff --git a/src/ver/step2.v b/src/ver/step2.v
new file mode 100644
index 0000000..70dfd22
--- /dev/null
+++ b/src/ver/step2.v
@@ -0,0 +1,34 @@
+`include "clockworks.v"
+
+module SOC (
+    input  CLK,        // system clock 
+    input  RESET,      // reset button
+    output [4:0] LEDS, // system LEDs
+    input  RXD,        // UART receive
+    output TXD         // UART transmit
+);
+
+   wire clk;    // internal clock
+   wire resetn; // internal reset signal, goes low on reset
+   
+   // A blinker that counts on 5 bits, wired to the 5 LEDs
+   reg [4:0] count = 0;
+   always @(posedge clk) begin
+      count <= !resetn ? 0 : count + 1;
+   end
+
+   // Clock gearbox (to let you see what happens)
+   // and reset circuitry (to workaround an
+   // initialization problem with Ice40)
+   Clockworks #(
+     .SLOW(21) // Divide clock frequency by 2^21
+   )CW(
+     .CLK(CLK),
+     .RESET(RESET),
+     .clk(clk),
+     .resetn(resetn)
+   );
+   
+   assign LEDS = count;
+   assign TXD  = 1'b0; // not used for now   
+endmodule