commit 617a2ff2c2fb7f4671d5681280254949b60be1d1
Author: u1 <u1@mpabi.pl>
Date:   Thu Nov 21 08:21:56 2024 +0100

    init

diff --git a/src/ver/step1.v b/src/ver/step1.v
new file mode 100644
index 0000000..9baa180
--- /dev/null
+++ b/src/ver/step1.v
@@ -0,0 +1,16 @@
+   module SOC (
+       input  CLK,        
+       input  RESET,      
+       output [4:0] LEDS, 
+       input  RXD,        
+       output TXD         
+   );
+
+   reg [4:0] count = 0;
+   always @(posedge CLK) begin
+      count <= count + 1;
+   end
+   assign LEDS = count;
+   assign TXD  = 1'b0; // not used for now
+
+   endmodule