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\title{Documentation of 1-Bit Full Adder in Verilog}
\author{Class 1i}
\date{}

\begin{document}

\maketitle

\tableofcontents
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\section{Introduction}
This document provides a detailed description of the 1-bit full adder module implemented in Verilog. A full adder is a digital circuit that performs the addition of binary numbers. In this design, the module takes three inputs: two single-bit binary values, \texttt{a} and \texttt{b}, and a carry-in bit, \texttt{carry\_in}. It produces two outputs: the sum (\texttt{sum}) and a carry-out bit (\texttt{carry\_out}).

\section{Module Description}
The 1-bit full adder module is defined in Verilog using the following interface:

\begin{verbatim}
module full_adder (
    input wire a,         // Input A
    input wire b,         // Input B
    input wire carry_in,  // Carry-in
    output wire sum,      // Sum output
    output wire carry_out // Carry-out
);
\end{verbatim}

\subsection{Inputs and Outputs}
\begin{itemize}
    \item \textbf{Input a}: The first binary input (single bit).
    \item \textbf{Input b}: The second binary input (single bit).
    \item \textbf{Input carry\_in}: The carry-in bit, representing any carry from the previous addition stage.
    \item \textbf{Output sum}: The sum result of inputs \texttt{a}, \texttt{b}, and \texttt{carry\_in}.
    \item \textbf{Output carry\_out}: The carry-out result, which is passed to the next stage if multiple bits are added.
\end{itemize}

\section{Operation}
The 1-bit full adder performs binary addition using the logic operations XOR, AND, and OR. The outputs are calculated as follows:

\begin{align*}
\text{sum} &= a \oplus b \oplus \text{carry\_in} \\
\text{carry\_out} &= (a \land b) \lor (\text{carry\_in} \land (a \oplus b))
\end{align*}

\subsection{Truth Table}
The truth table for the 1-bit full adder is shown below:

\begin{center}
\begin{tabular}{|c|c|c|c|c|}
\hline
\textbf{a} & \textbf{b} & \textbf{carry\_in} & \textbf{sum} & \textbf{carry\_out} \\
\hline
0 & 0 & 0 & 0 & 0 \\
0 & 0 & 1 & 1 & 0 \\
0 & 1 & 0 & 1 & 0 \\
0 & 1 & 1 & 0 & 1 \\
1 & 0 & 0 & 1 & 0 \\
1 & 0 & 1 & 0 & 1 \\
1 & 1 & 0 & 0 & 1 \\
1 & 1 & 1 & 1 & 1 \\
\hline
\end{tabular}
\end{center}

\section{Implementation}
The Verilog implementation of the full adder uses logical operations to compute the sum and carry-out as shown below:

\begin{verbatim}
module full_adder (
    input wire a,
    input wire b,
    input wire carry_in,
    output wire sum,
    output wire carry_out
);
    assign sum = a ^ b ^ carry_in;
    assign carry_out = (a & b) | (carry_in & (a ^ b));
endmodule
\end{verbatim}

\section{Parameterization}
To make this module more versatile, we can parameterize it to allow the user to define different bit widths. Here is an example of a parameterized full adder that allows for a multi-bit input:

\begin{verbatim}
module full_adder #(
    parameter WIDTH = 1
) (
    input wire [WIDTH-1:0] a,
    input wire [WIDTH-1:0] b,
    input wire carry_in,
    output wire [WIDTH-1:0] sum,
    output wire carry_out
);
    assign {carry_out, sum} = a + b + carry_in;
endmodule
\end{verbatim}

In this parameterized version, \texttt{WIDTH} is a parameter that specifies the number of bits. The module can handle inputs of any width by changing the \texttt{WIDTH} value when instantiating the module.

\section{Compilation and Synthesis Instructions}
To compile and synthesize the Verilog code for the iCEBreaker FPGA, follow these steps:

\begin{enumerate}
    \item **Save the Verilog file**: Save the Verilog code as \texttt{sum.v} and the pin configuration as \texttt{sum.pcf}.
    \item **Synthesize with Yosys**:
    \begin{verbatim}
    yosys -p "synth_ice40 -top full_adder -json sum.json" sum.v
    \end{verbatim}
    This command synthesizes the Verilog code for the iCE40 FPGA architecture and outputs a JSON netlist.
    
    \item **Place and route with nextpnr**:
    \begin{verbatim}
    nextpnr-ice40 --up5k --package sg48 --pcf sum.pcf --json sum.json --asc sum.asc
    \end{verbatim}
    This command places and routes the design for the UP5K model of the iCE40 FPGA.

    \item **Generate a binary file with icepack**:
    \begin{verbatim}
    icepack sum.asc sum.bin
    \end{verbatim}
    This converts the ASCII file (\texttt{.asc}) to a binary file (\texttt{.bin}) for programming the FPGA.

    \item **Program the FPGA with iceprog**:
    \begin{verbatim}
    iceprog sum.bin
    \end{verbatim}
    This command uploads the binary file to the iCEBreaker FPGA board.
\end{enumerate}

\section{Testing}
To verify the correctness of the full adder, the module can be tested with all combinations of inputs (as shown in the truth table) to ensure that the sum and carry-out values are produced correctly. A testbench in Verilog can be created to apply these inputs and observe the outputs.

\section{Conclusion}
This document provides a detailed overview of the 1-bit full adder module implemented in Verilog, including its interface, operation, and logic. This module is fundamental in digital systems, especially for implementing multi-bit adders and arithmetic operations in larger circuits.

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