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 \section{Introduction}
 This document provides a detailed description of the 1-bit full adder module implemented in Verilog. A full adder is a digital circuit that performs the addition of binary numbers. In this design, the module takes three inputs: two single-bit binary values, \texttt{a} and \texttt{b}, and a carry-in bit, \texttt{carry\_in}. It produces two outputs: the sum (\texttt{sum}) and a carry-out bit (\texttt{carry\_out}).
 
+\section*{Installing Yosys and nextpnr from Source}
+
+Yosys and nextpnr are open-source tools for digital synthesis and place-and-route. The following steps guide you through building and installing these tools from source.
+
+\subsection*{Yosys Installation}
+
+\begin{enumerate}
+    \item \textbf{Clone the Yosys repository:} Begin by cloning the Yosys repository from GitHub.
+    \begin{verbatim}
+    git clone https://github.com/YosysHQ/yosys.git
+    \end{verbatim}
+
+    \item \textbf{Install dependencies:} Make sure all necessary dependencies are installed by running:
+    \begin{verbatim}
+    sudo apt-get install build-essential clang lld bison flex \
+    libreadline-dev gawk tcl-dev libffi-dev git \
+    graphviz xdot pkg-config python3 libboost-system-dev \
+    libboost-python-dev libboost-filesystem-dev zlib1g-dev
+    \end{verbatim}
+
+    \item \textbf{Configure Yosys to use Clang:} In the Yosys directory, configure it to use the Clang compiler.
+    \begin{verbatim}
+    make config-clang
+    \end{verbatim}
+
+    \item \textbf{Initialize submodules:} Make sure all Git submodules are up to date.
+    \begin{verbatim}
+    git submodule update --init
+    \end{verbatim}
+
+    \item \textbf{Build Yosys:} Compile Yosys using multiple threads.
+    \begin{verbatim}
+    make -j32
+    \end{verbatim}
+
+    \item \textbf{Install Yosys:} After the build is complete, install Yosys system-wide.
+    \begin{verbatim}
+    sudo make install
+    \end{verbatim}
+\end{enumerate}
+
+\subsection*{nextpnr Installation}
+
+\begin{enumerate}
+    \item \textbf{Navigate back to the parent directory:}
+    \begin{verbatim}
+    cd ../
+    \end{verbatim}
+
+    \item \textbf{Clone the nextpnr repository:} Download the nextpnr repository from GitHub.
+    \begin{verbatim}
+    git clone https://github.com/YosysHQ/nextpnr
+    \end{verbatim}
+
+    \item \textbf{Install cmake:} Install cmake, which is required to build nextpnr.
+    \begin{verbatim}
+    sudo apt install cmake
+    \end{verbatim}
+
+    \item \textbf{Configure nextpnr for the iCE40 architecture:} In the nextpnr directory, run cmake with the iCE40 architecture option.
+    \begin{verbatim}
+    cmake . -DARCH=ice40
+    \end{verbatim}
+
+    \item \textbf{Build nextpnr:} Compile nextpnr using all available processor cores.
+    \begin{verbatim}
+    make -j$(nproc)
+    \end{verbatim}
+
+    \item \textbf{Install nextpnr:} Once the build completes, install nextpnr system-wide.
+    \begin{verbatim}
+    sudo make install
+    \end{verbatim}
+\end{enumerate}
+
+\subsection*{Verification}
+
+After installing Yosys and nextpnr, verify the installation by running:
+\begin{verbatim}
+yosys -V
+nextpnr-ice40 --help
+\end{verbatim}
+These commands should display version or help information, confirming that the tools are correctly installed.
+
+
 \section{Module Description}
 The 1-bit full adder module is defined in Verilog using the following interface: