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\documentclass[a4paper,12pt]{article}
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\usepackage[utf8]{inputenc}
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\usepackage{amsmath}
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\usepackage{hyperref}
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\title{Documentation of 1-Bit Full Adder in Verilog}
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\author{Class 1i}
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\date{}
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\begin{document}
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\maketitle
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\tableofcontents
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\newpage
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\section{Introduction}
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This document provides a detailed description of the 1-bit full adder module implemented in Verilog. A full adder is a digital circuit that performs the addition of binary numbers. In this design, the module takes three inputs: two single-bit binary values, \texttt{a} and \texttt{b}, and a carry-in bit, \texttt{carry\_in}. It produces two outputs: the sum (\texttt{sum}) and a carry-out bit (\texttt{carry\_out}).
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\section{Module Description}
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The 1-bit full adder module is defined in Verilog using the following interface:
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\begin{verbatim}
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module full_adder (
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input wire a, // Input A
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input wire b, // Input B
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input wire carry_in, // Carry-in
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output wire sum, // Sum output
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output wire carry_out // Carry-out
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);
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\end{verbatim}
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\subsection{Inputs and Outputs}
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\begin{itemize}
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\item \textbf{Input a}: The first binary input (single bit).
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\item \textbf{Input b}: The second binary input (single bit).
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\item \textbf{Input carry\_in}: The carry-in bit, representing any carry from the previous addition stage.
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\item \textbf{Output sum}: The sum result of inputs \texttt{a}, \texttt{b}, and \texttt{carry\_in}.
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\item \textbf{Output carry\_out}: The carry-out result, which is passed to the next stage if multiple bits are added.
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\end{itemize}
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\section{Operation}
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The 1-bit full adder performs binary addition using the logic operations XOR, AND, and OR. The outputs are calculated as follows:
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\begin{align*}
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\text{sum} &= a \oplus b \oplus \text{carry\_in} \\
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\text{carry\_out} &= (a \land b) \lor (\text{carry\_in} \land (a \oplus b))
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\end{align*}
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\subsection{Truth Table}
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The truth table for the 1-bit full adder is shown below:
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\begin{center}
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\begin{tabular}{|c|c|c|c|c|}
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\hline
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\textbf{a} & \textbf{b} & \textbf{carry\_in} & \textbf{sum} & \textbf{carry\_out} \\
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\hline
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0 & 0 & 0 & 0 & 0 \\
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0 & 0 & 1 & 1 & 0 \\
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0 & 1 & 0 & 1 & 0 \\
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0 & 1 & 1 & 0 & 1 \\
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1 & 0 & 0 & 1 & 0 \\
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1 & 0 & 1 & 0 & 1 \\
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1 & 1 & 0 & 0 & 1 \\
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1 & 1 & 1 & 1 & 1 \\
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\hline
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\end{tabular}
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\end{center}
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\section{Implementation}
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The Verilog implementation of the full adder uses logical operations to compute the sum and carry-out as shown below:
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\begin{verbatim}
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module full_adder (
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input wire a,
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input wire b,
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input wire carry_in,
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output wire sum,
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output wire carry_out
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);
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assign sum = a ^ b ^ carry_in;
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assign carry_out = (a & b) | (carry_in & (a ^ b));
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endmodule
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\end{verbatim}
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\section{Parameterization}
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To make this module more versatile, we can parameterize it to allow the user to define different bit widths. Here is an example of a parameterized full adder that allows for a multi-bit input:
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\begin{verbatim}
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module full_adder #(
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parameter WIDTH = 1
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) (
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input wire [WIDTH-1:0] a,
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input wire [WIDTH-1:0] b,
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input wire carry_in,
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output wire [WIDTH-1:0] sum,
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output wire carry_out
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);
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assign {carry_out, sum} = a + b + carry_in;
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endmodule
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\end{verbatim}
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In this parameterized version, \texttt{WIDTH} is a parameter that specifies the number of bits. The module can handle inputs of any width by changing the \texttt{WIDTH} value when instantiating the module.
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\section{Compilation and Synthesis Instructions}
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To compile and synthesize the Verilog code for the iCEBreaker FPGA, follow these steps:
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\begin{enumerate}
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\item **Save the Verilog file**: Save the Verilog code as \texttt{sum.v} and the pin configuration as \texttt{sum.pcf}.
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\item **Synthesize with Yosys**:
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\begin{verbatim}
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yosys -p "synth_ice40 -top full_adder -json sum.json" sum.v
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\end{verbatim}
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This command synthesizes the Verilog code for the iCE40 FPGA architecture and outputs a JSON netlist.
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\item **Place and route with nextpnr**:
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\begin{verbatim}
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nextpnr-ice40 --up5k --package sg48 --pcf sum.pcf --json sum.json --asc sum.asc
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\end{verbatim}
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This command places and routes the design for the UP5K model of the iCE40 FPGA.
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\item **Generate a binary file with icepack**:
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\begin{verbatim}
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icepack sum.asc sum.bin
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\end{verbatim}
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This converts the ASCII file (\texttt{.asc}) to a binary file (\texttt{.bin}) for programming the FPGA.
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\item **Program the FPGA with iceprog**:
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\begin{verbatim}
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iceprog sum.bin
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\end{verbatim}
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This command uploads the binary file to the iCEBreaker FPGA board.
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\end{enumerate}
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\section{Testing}
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To verify the correctness of the full adder, the module can be tested with all combinations of inputs (as shown in the truth table) to ensure that the sum and carry-out values are produced correctly. A testbench in Verilog can be created to apply these inputs and observe the outputs.
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\section{Conclusion}
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This document provides a detailed overview of the 1-bit full adder module implemented in Verilog, including its interface, operation, and logic. This module is fundamental in digital systems, especially for implementing multi-bit adders and arithmetic operations in larger circuits.
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\end{document}
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set_io a 12 # Przycisk A (Button 3)
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set_io b 11 # Przycisk B (Button 2)
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set_io carry_in 10 # Przycisk Carry-in (Button 1)
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set_io sum 39 # Wyjście suma na diodzie L1
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set_io carry_out 40 # Wyjście carry-out na diodzie L2
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set_io l3 41 # Dioda L3 dla wejścia B
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set_io l4 42 # Dioda L4 dla carry_in
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set_io l5 37 # Dioda L5 dla wejścia A
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module full_adder (
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input wire a, // Wejście A (przycisk)
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input wire b, // Wejście B (przycisk)
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input wire carry_in, // Wejście przeniesienia (przycisk)
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output wire sum, // Wyjście suma (dioda)
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output wire carry_out, // Wyjście przeniesienia (dioda)
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output wire l3, // L3 dla B
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output wire l4, // L4 dla carry_in
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output wire l5 // L5 dla A
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);
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assign sum = a ^ b ^ carry_in; // Obliczenie sumy
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assign carry_out = (a & b) | (carry_in & (a ^ b)); // Obliczenie przeniesienia
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assign l5 = a; // L5 pokazuje stan A
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assign l3 = b; // L3 pokazuje stan B
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assign l4 = carry_in; // L4 pokazuje stan carry_in
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endmodule
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