\title{Documentation of 1-Bit Full Adder in Verilog}
\author{Class 1i}
\date{}
\begin{document}
\maketitle
\tableofcontents
\newpage
\section{Introduction}
This document provides a detailed description of the 1-bit full adder module implemented in Verilog. A full adder is a digital circuit that performs the addition of binary numbers. In this design, the module takes three inputs: two single-bit binary values, \texttt{a} and \texttt{b}, and a carry-in bit, \texttt{carry\_in}. It produces two outputs: the sum (\texttt{sum}) and a carry-out bit (\texttt{carry\_out}).
\section*{Installing Yosys and nextpnr from Source}
Yosys and nextpnr are open-source tools for digital synthesis and place-and-route. The following steps guide you through building and installing these tools from source.
\subsection*{Yosys Installation}
\begin{enumerate}
\item\textbf{Clone the Yosys repository:} Begin by cloning the Yosys repository from GitHub.
\item\textbf{Configure nextpnr for the iCE40 architecture:} In the nextpnr directory, run cmake with the iCE40 architecture option. This will also integrate Icestorm.
The Verilog implementation of the full adder uses logical operations to compute the sum and carry-out as shown below:
\begin{verbatim}
module full_adder (
input wire a,
input wire b,
input wire carry_in,
output wire sum,
output wire carry_out
);
assign sum = a ^ b ^ carry_in;
assign carry_out = (a & b) | (carry_in & (a ^ b));
endmodule
\end{verbatim}
\section{Parameterization}
To make this module more versatile, we can parameterize it to allow the user to define different bit widths. Here is an example of a parameterized full adder that allows for a multi-bit input:
\begin{verbatim}
module full_adder #(
parameter WIDTH = 1
) (
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
input wire carry_in,
output wire [WIDTH-1:0] sum,
output wire carry_out
);
assign {carry_out, sum} = a + b + carry_in;
endmodule
\end{verbatim}
In this parameterized version, \texttt{WIDTH} is a parameter that specifies the number of bits. The module can handle inputs of any width by changing the \texttt{WIDTH} value when instantiating the module.
\section{Compilation and Synthesis Instructions}
To compile and synthesize the Verilog code for the iCEBreaker FPGA, follow these steps:
\begin{enumerate}
\item **Save the Verilog file**: Save the Verilog code as \texttt{sum.v} and the pin configuration as \texttt{sum.pcf}.
This command places and routes the design for the UP5K model of the iCE40 FPGA.
\item **Generate a binary file with icepack**:
\begin{verbatim}
icepack sum.asc sum.bin
\end{verbatim}
This converts the ASCII file (\texttt{.asc}) to a binary file (\texttt{.bin}) for programming the FPGA.
\item **Program the FPGA with iceprog**:
\begin{verbatim}
iceprog sum.bin
\end{verbatim}
This command uploads the binary file to the iCEBreaker FPGA board.
\end{enumerate}
\section{Testing}
To verify the correctness of the full adder, the module can be tested with all combinations of inputs (as shown in the truth table) to ensure that the sum and carry-out values are produced correctly. A testbench in Verilog can be created to apply these inputs and observe the outputs.
\section{Conclusion}
This document provides a detailed overview of the 1-bit full adder module implemented in Verilog, including its interface, operation, and logic. This module is fundamental in digital systems, especially for implementing multi-bit adders and arithmetic operations in larger circuits.
