544 lines
17 KiB
Scala
544 lines
17 KiB
Scala
package vexriscv.demo
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba3.apb._
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.bus.simple.PipelinedMemoryBus
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.spi.ddr.SpiXdrMaster
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import spinal.lib.com.uart._
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import spinal.lib.io.{InOutWrapper, TriStateArray}
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import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer}
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import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
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import vexriscv.plugin._
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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import spinal.lib.com.spi.ddr._
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import spinal.lib.bus.simple._
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import scala.collection.mutable.ArrayBuffer
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import scala.collection.Seq
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/**
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* Created by PIC32F_USER on 28/07/2017.
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*
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* Murax is a very light SoC which could work without any external component.
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* - ICE40-hx8k + icestorm => 53 Mhz, 2142 LC
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* - 0.37 DMIPS/Mhz
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* - 8 kB of on-chip ram
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* - JTAG debugger (eclipse/GDB/openocd ready)
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* - Interrupt support
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* - APB bus for peripherals
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* - 32 GPIO pin
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* - one 16 bits prescaler, two 16 bits timers
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* - one UART with tx/rx fifo
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*/
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case class MuraxConfig(coreFrequency : HertzNumber,
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onChipRamSize : BigInt,
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onChipRamHexFile : String,
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pipelineDBus : Boolean,
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pipelineMainBus : Boolean,
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pipelineApbBridge : Boolean,
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gpioWidth : Int,
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uartCtrlConfig : UartCtrlMemoryMappedConfig,
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xipConfig : SpiXdrMasterCtrl.MemoryMappingParameters,
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hardwareBreakpointCount : Int,
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cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){
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require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
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val genXip = xipConfig != null
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}
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object MuraxConfig{
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def default : MuraxConfig = default(false, false)
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def default(withXip : Boolean = false, bigEndian : Boolean = false) = MuraxConfig(
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coreFrequency = 12 MHz,
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onChipRamSize = 128 kB,
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onChipRamHexFile = null,
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pipelineDBus = true,
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pipelineMainBus = false,
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pipelineApbBridge = true,
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gpioWidth = 32,
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xipConfig = ifGen(withXip) (SpiXdrMasterCtrl.MemoryMappingParameters(
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SpiXdrMasterCtrl.Parameters(8, 12, SpiXdrParameter(2, 2, 1)).addFullDuplex(0,1,false),
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cmdFifoDepth = 32,
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rspFifoDepth = 32,
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xip = SpiXdrMasterCtrl.XipBusParameters(addressWidth = 24, lengthWidth = 2)
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)),
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hardwareBreakpointCount = if(withXip) 3 else 0,
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cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel
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new IBusSimplePlugin(
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resetVector = if(withXip) 0xF001E000l else 0x00000000l,
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cmdForkOnSecondStage = true,
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cmdForkPersistence = withXip, //Required by the Xip controller
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prediction = NONE,
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catchAccessFault = false,
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compressedGen = false,
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bigEndian = bigEndian
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false,
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earlyInjection = false,
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bigEndian = bigEndian
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),
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new CsrPlugin(CsrPluginConfig.smallest(mtvecInit = if(withXip) 0xE0040020l else 0x00000020l)),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = false
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false
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),
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new YamlPlugin("cpu0.yaml")
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),
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uartCtrlConfig = UartCtrlMemoryMappedConfig(
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uartCtrlConfig = UartCtrlGenerics(
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dataWidthMax = 8,
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clockDividerWidth = 20,
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preSamplingSize = 1,
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samplingSize = 3,
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postSamplingSize = 1
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),
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initConfig = UartCtrlInitConfig(
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baudrate = 115200,
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dataLength = 7, //7 => 8 bits
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parity = UartParityType.NONE,
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stop = UartStopType.ONE
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),
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busCanWriteClockDividerConfig = false,
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busCanWriteFrameConfig = false,
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txFifoDepth = 16,
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rxFifoDepth = 16
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)
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)
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def fast = {
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val config = default
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//Replace HazardSimplePlugin to get datapath bypass
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config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[HazardSimplePlugin])) = new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true
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)
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// config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[LightShifterPlugin])) = new FullBarrelShifterPlugin()
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config
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}
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}
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case class Murax(config : MuraxConfig) extends Component{
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import config._
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val io = new Bundle {
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//Clocks / reset
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val asyncReset = in Bool()
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val mainClk = in Bool()
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//Main components IO
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val jtag = slave(Jtag())
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//Peripherals IO
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val gpioA = master(TriStateArray(gpioWidth bits))
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val uart = master(Uart())
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val xip = ifGen(genXip)(master(SpiXdrMaster(xipConfig.ctrl.spi)))
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}
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val resetCtrlClockDomain = ClockDomain(
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clock = io.mainClk,
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config = ClockDomainConfig(
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resetKind = BOOT
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)
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)
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val resetCtrl = new ClockingArea(resetCtrlClockDomain) {
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val mainClkResetUnbuffered = False
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//Implement an counter to keep the reset axiResetOrder high 64 cycles
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// Also this counter will automatically do a reset when the system boot.
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val systemClkResetCounter = Reg(UInt(6 bits)) init(0)
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when(systemClkResetCounter =/= U(systemClkResetCounter.range -> true)){
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systemClkResetCounter := systemClkResetCounter + 1
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mainClkResetUnbuffered := True
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}
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when(BufferCC(io.asyncReset)){
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systemClkResetCounter := 0
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}
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//Create all reset used later in the design
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val mainClkReset = RegNext(mainClkResetUnbuffered)
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val systemReset = RegNext(mainClkResetUnbuffered)
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}
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val systemClockDomain = ClockDomain(
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clock = io.mainClk,
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reset = resetCtrl.systemReset,
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frequency = FixedFrequency(coreFrequency)
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)
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val debugClockDomain = ClockDomain(
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clock = io.mainClk,
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reset = resetCtrl.mainClkReset,
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frequency = FixedFrequency(coreFrequency)
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)
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val system = new ClockingArea(systemClockDomain) {
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val pipelinedMemoryBusConfig = PipelinedMemoryBusConfig(
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addressWidth = 32,
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dataWidth = 32
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)
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val bigEndianDBus = config.cpuPlugins.exists(_ match{ case plugin : DBusSimplePlugin => plugin.bigEndian case _ => false})
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//Arbiter of the cpu dBus/iBus to drive the mainBus
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//Priority to dBus, !! cmd transactions can change on the fly !!
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val mainBusArbiter = new MuraxMasterArbiter(pipelinedMemoryBusConfig, bigEndianDBus)
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//Instanciate the CPU
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val cpu = new VexRiscv(
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config = VexRiscvConfig(
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plugins = cpuPlugins += new DebugPlugin(debugClockDomain, hardwareBreakpointCount)
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)
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)
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//Checkout plugins used to instanciate the CPU to connect them to the SoC
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val timerInterrupt = False
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val externalInterrupt = False
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for(plugin <- cpu.plugins) plugin match{
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case plugin : IBusSimplePlugin =>
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mainBusArbiter.io.iBus.cmd <> plugin.iBus.cmd
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mainBusArbiter.io.iBus.rsp <> plugin.iBus.rsp
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case plugin : DBusSimplePlugin => {
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if(!pipelineDBus)
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mainBusArbiter.io.dBus <> plugin.dBus
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else {
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mainBusArbiter.io.dBus.cmd << plugin.dBus.cmd.halfPipe()
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mainBusArbiter.io.dBus.rsp <> plugin.dBus.rsp
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}
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}
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case plugin : CsrPlugin => {
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plugin.externalInterrupt := externalInterrupt
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plugin.timerInterrupt := timerInterrupt
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}
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case plugin : DebugPlugin => plugin.debugClockDomain{
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resetCtrl.systemReset setWhen(RegNext(plugin.io.resetOut))
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io.jtag <> plugin.io.bus.fromJtag()
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}
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case _ =>
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}
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//****** MainBus slaves ********
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val mainBusMapping = ArrayBuffer[(PipelinedMemoryBus,SizeMapping)]()
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val ram = new MuraxPipelinedMemoryBusRam(
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onChipRamSize = onChipRamSize,
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onChipRamHexFile = onChipRamHexFile,
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pipelinedMemoryBusConfig = pipelinedMemoryBusConfig,
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bigEndian = bigEndianDBus
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)
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mainBusMapping += ram.io.bus -> (0x00000000l, onChipRamSize)
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val apbBridge = new PipelinedMemoryBusToApbBridge(
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apb3Config = Apb3Config(
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addressWidth = 20,
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dataWidth = 32
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),
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pipelineBridge = pipelineApbBridge,
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pipelinedMemoryBusConfig = pipelinedMemoryBusConfig
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)
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mainBusMapping += apbBridge.io.pipelinedMemoryBus -> (0xF0000000l, 1 MB)
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//******** APB peripherals *********
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val apbMapping = ArrayBuffer[(Apb3, SizeMapping)]()
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val gpioACtrl = Apb3Gpio(gpioWidth = gpioWidth, withReadSync = true)
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io.gpioA <> gpioACtrl.io.gpio
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apbMapping += gpioACtrl.io.apb -> (0x00000, 4 kB)
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val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
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uartCtrl.io.uart <> io.uart
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externalInterrupt setWhen(uartCtrl.io.interrupt)
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apbMapping += uartCtrl.io.apb -> (0x10000, 4 kB)
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val timer = new MuraxApb3Timer()
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timerInterrupt setWhen(timer.io.interrupt)
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apbMapping += timer.io.apb -> (0x20000, 4 kB)
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val xip = ifGen(genXip)(new Area{
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val ctrl = Apb3SpiXdrMasterCtrl(xipConfig)
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ctrl.io.spi <> io.xip
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externalInterrupt setWhen(ctrl.io.interrupt)
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apbMapping += ctrl.io.apb -> (0x1F000, 4 kB)
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val accessBus = new PipelinedMemoryBus(PipelinedMemoryBusConfig(24,32))
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mainBusMapping += accessBus -> (0xE0000000l, 16 MB)
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ctrl.io.xip.fromPipelinedMemoryBus() << accessBus
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val bootloader = Apb3Rom("src/main/c/murax/xipBootloader/crt.bin")
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apbMapping += bootloader.io.apb -> (0x1E000, 4 kB)
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})
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//******** Memory mappings *********
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val apbDecoder = Apb3Decoder(
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master = apbBridge.io.apb,
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slaves = apbMapping.toSeq
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)
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val mainBusDecoder = new Area {
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val logic = new MuraxPipelinedMemoryBusDecoder(
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master = mainBusArbiter.io.masterBus,
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specification = mainBusMapping.toSeq,
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pipelineMaster = pipelineMainBus
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)
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}
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}
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}
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object Murax{
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def main(args: Array[String]) {
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SpinalVerilog(Murax(MuraxConfig.default))
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}
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}
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object MuraxCfu{
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def main(args: Array[String]) {
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SpinalVerilog{
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val config = MuraxConfig.default
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config.cpuPlugins += new CfuPlugin(
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stageCount = 1,
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allowZeroLatency = true,
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encodings = List(
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CfuPluginEncoding (
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instruction = M"-------------------------0001011",
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functionId = List(14 downto 12),
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input2Kind = CfuPlugin.Input2Kind.RS
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)
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),
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busParameter = CfuBusParameter(
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CFU_VERSION = 0,
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CFU_INTERFACE_ID_W = 0,
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CFU_FUNCTION_ID_W = 3,
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CFU_REORDER_ID_W = 0,
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CFU_REQ_RESP_ID_W = 0,
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CFU_INPUTS = 2,
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CFU_INPUT_DATA_W = 32,
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CFU_OUTPUTS = 1,
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CFU_OUTPUT_DATA_W = 32,
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CFU_FLOW_REQ_READY_ALWAYS = false,
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CFU_FLOW_RESP_READY_ALWAYS = false,
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CFU_WITH_STATUS = true,
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CFU_RAW_INSN_W = 32,
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CFU_CFU_ID_W = 4,
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CFU_STATE_INDEX_NUM = 5
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)
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)
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val toplevel = Murax(config)
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toplevel.rework {
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for (plugin <- toplevel.system.cpu.plugins) plugin match {
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case plugin: CfuPlugin => plugin.bus.toIo().setName("miaou")
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case _ =>
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}
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}
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toplevel
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}
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}
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}
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object Murax_iCE40_hx8k_breakout_board_xip{
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case class SB_GB() extends BlackBox{
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val USER_SIGNAL_TO_GLOBAL_BUFFER = in Bool()
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val GLOBAL_BUFFER_OUTPUT = out Bool()
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}
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case class SB_IO_SCLK() extends BlackBox{
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addGeneric("PIN_TYPE", B"010000")
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val PACKAGE_PIN = out Bool()
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val OUTPUT_CLK = in Bool()
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val CLOCK_ENABLE = in Bool()
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val D_OUT_0 = in Bool()
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val D_OUT_1 = in Bool()
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setDefinitionName("SB_IO")
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}
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case class SB_IO_DATA() extends BlackBox{
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addGeneric("PIN_TYPE", B"110000")
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val PACKAGE_PIN = inout(Analog(Bool))
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val CLOCK_ENABLE = in Bool()
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val INPUT_CLK = in Bool()
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val OUTPUT_CLK = in Bool()
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val OUTPUT_ENABLE = in Bool()
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val D_OUT_0 = in Bool()
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val D_OUT_1 = in Bool()
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val D_IN_0 = out Bool()
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val D_IN_1 = out Bool()
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setDefinitionName("SB_IO")
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}
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case class Murax_iCE40_hx8k_breakout_board_xip() extends Component{
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val io = new Bundle {
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val mainClk = in Bool()
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val jtag_tck = in Bool()
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val jtag_tdi = in Bool()
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val jtag_tdo = out Bool()
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val jtag_tms = in Bool()
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val uart_txd = out Bool()
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val uart_rxd = in Bool()
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val mosi = inout(Analog(Bool))
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val miso = inout(Analog(Bool))
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val sclk = out Bool()
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val spis = out Bool()
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val led = out Bits(8 bits)
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}
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val murax = Murax(MuraxConfig.default(withXip = true).copy(onChipRamSize = 8 kB))
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murax.io.asyncReset := False
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val mainClkBuffer = SB_GB()
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mainClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.mainClk
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mainClkBuffer.GLOBAL_BUFFER_OUTPUT <> murax.io.mainClk
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val jtagClkBuffer = SB_GB()
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jtagClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.jtag_tck
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jtagClkBuffer.GLOBAL_BUFFER_OUTPUT <> murax.io.jtag.tck
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io.led <> murax.io.gpioA.write(7 downto 0)
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murax.io.jtag.tdi <> io.jtag_tdi
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murax.io.jtag.tdo <> io.jtag_tdo
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murax.io.jtag.tms <> io.jtag_tms
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murax.io.gpioA.read <> 0
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murax.io.uart.txd <> io.uart_txd
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murax.io.uart.rxd <> io.uart_rxd
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val xip = new ClockingArea(murax.systemClockDomain) {
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RegNext(murax.io.xip.ss.asBool) <> io.spis
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val sclkIo = SB_IO_SCLK()
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sclkIo.PACKAGE_PIN <> io.sclk
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sclkIo.CLOCK_ENABLE := True
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sclkIo.OUTPUT_CLK := ClockDomain.current.readClockWire
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sclkIo.D_OUT_0 <> murax.io.xip.sclk.write(0)
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sclkIo.D_OUT_1 <> RegNext(murax.io.xip.sclk.write(1))
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val datas = for ((data, pin) <- (murax.io.xip.data, List(io.mosi, io.miso)).zipped) yield new Area {
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val dataIo = SB_IO_DATA()
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dataIo.PACKAGE_PIN := pin
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dataIo.CLOCK_ENABLE := True
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dataIo.OUTPUT_CLK := ClockDomain.current.readClockWire
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dataIo.OUTPUT_ENABLE <> data.writeEnable
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dataIo.D_OUT_0 <> data.write(0)
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dataIo.D_OUT_1 <> RegNext(data.write(1))
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dataIo.INPUT_CLK := ClockDomain.current.readClockWire
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data.read(0) := dataIo.D_IN_0
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data.read(1) := RegNext(dataIo.D_IN_1)
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}
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}
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}
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def main(args: Array[String]) {
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SpinalVerilog(Murax_iCE40_hx8k_breakout_board_xip())
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}
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}
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object MuraxDhrystoneReady{
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def main(args: Array[String]) {
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SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB)))
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}
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}
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object MuraxDhrystoneReadyMulDivStatic{
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def main(args: Array[String]) {
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SpinalVerilog({
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val config = MuraxConfig.fast.copy(onChipRamSize = 256 kB)
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config.cpuPlugins += new MulPlugin
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config.cpuPlugins += new DivPlugin
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config.cpuPlugins.remove(config.cpuPlugins.indexWhere(_.isInstanceOf[BranchPlugin]))
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config.cpuPlugins +=new BranchPlugin(
|
|
earlyBranch = false,
|
|
catchAddressMisaligned = false
|
|
)
|
|
config.cpuPlugins += new IBusSimplePlugin(
|
|
resetVector = 0x00000000l,
|
|
cmdForkOnSecondStage = true,
|
|
cmdForkPersistence = false,
|
|
prediction = STATIC,
|
|
catchAccessFault = false,
|
|
compressedGen = false
|
|
)
|
|
config.cpuPlugins.remove(config.cpuPlugins.indexWhere(_.isInstanceOf[LightShifterPlugin]))
|
|
config.cpuPlugins += new FullBarrelShifterPlugin
|
|
Murax(config)
|
|
})
|
|
}
|
|
}
|
|
|
|
//Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
|
|
object MuraxWithRamInit{
|
|
def main(args: Array[String]) {
|
|
SpinalVerilog(Murax(MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")))
|
|
}
|
|
}
|
|
|
|
object Murax_arty{
|
|
def main(args: Array[String]) {
|
|
val hex = "src/main/c/murax/hello_world/build/hello_world.hex"
|
|
SpinalVerilog(Murax(MuraxConfig.default(false).copy(coreFrequency = 100 MHz,onChipRamSize = 32 kB, onChipRamHexFile = hex)))
|
|
}
|
|
}
|
|
|
|
|
|
object MuraxAsicBlackBox extends App{
|
|
println("Warning this soc do not has any rom to boot on.")
|
|
val config = SpinalConfig()
|
|
config.addStandardMemBlackboxing(blackboxAll)
|
|
config.generateVerilog(Murax(MuraxConfig.default()))
|
|
}
|
|
|