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f9a738ff3f
| Author | SHA1 | Date |
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 borysr
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f9a738ff3f | |
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borysr
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3a9144c498 | |
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borysr
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0c3db919a2 | |
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borysr
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f8380b5835 |
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@ -1,81 +0,0 @@
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ARCH=riscv64-unknown-elf
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GNU_DIR=$(HOME)/riscv/riscv/
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GNU_BIN=$(GNU_DIR)/bin
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CC=$(GNU_BIN)/$(ARCH)-gcc
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CXX=$(GNU_BIN)/$(ARCH)-g++
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AS=$(GNU_BIN)/$(ARCH)-as
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LD=$(GNU_BIN)/$(ARCH)-ld
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OBJCOPY=$(GNU_BIN)/$(ARCH)-objcopy
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OBJDUMP=$(GNU_BIN)/$(ARCH)-objdump
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SIZE=$(GNU_BIN)/$(ARCH)-size
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AR=$(GNU_BIN)/$(ARCH)-ar
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RANLIB=$(GNU_BIN)/$(ARCH)-ranlib
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CFLAGS+=-ffreestanding
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CFLAGS+=-fno-pic
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CFLAGS+=-march=rv32i -mabi=ilp32
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CFLAGS+= -g
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LDFLAGS+=-nostdlib
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LDFLAGS+=-Wl,-Ttext=0x00000000
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# see: https://github.com/riscv/riscv-gcc/issues/120
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#LDFLAGS+=-Wl,--no-relax
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ASFLAGS+=$(CFLAGS)
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CXXFLAGS+=$(CFLAGS)
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CLEAN_DIRS=$(SUBDIRS:%=clean-%)
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ALL_DIRS=$(SUBDIRS:%=all-%)
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OBJDUMPFLAGS+=-Mnumeric,no-aliases
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.PHONY: all clean world $(CLEAN_DIRS) $(ALL_DIRS)
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%.bin : %
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$(OBJCOPY) $< -O binary $@
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%.lst : %
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$(OBJDUMP) $(OBJDUMPFLAGS) -dr --disassemble-all $< > $<.lst
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% : %.o
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$(LINK.cc) $(LDFLAGS) -o $@ $^ $(LDLIBS)
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$(SIZE) -x -A $@
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%.s: %.c
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$(COMPILE.c) -S -o $@ $<
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%.s: %.cc
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$(COMPILE.cc) -S -o $@ $<
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%.o: %.c
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$(COMPILE.c) -o $@ $<
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%.o: %.cc
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$(COMPILE.cc) -o $@ $<
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%.srec: %
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$(OBJCOPY) $< -O srec $@
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all:: $(ALL_DIRS)
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clean:: $(CLEAN_DIRS)
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$(ALL_DIRS)::
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$(MAKE) -C $(@:all-%=%) all
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$(CLEAN_DIRS)::
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$(MAKE) -C $(@:clean-%=%) clean
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world:: clean all
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543
cpp/Murax.scala
543
cpp/Murax.scala
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@ -1,543 +0,0 @@
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package vexriscv.demo
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba3.apb._
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import spinal.lib.bus.misc.SizeMapping
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import spinal.lib.bus.simple.PipelinedMemoryBus
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.spi.ddr.SpiXdrMaster
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import spinal.lib.com.uart._
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import spinal.lib.io.{InOutWrapper, TriStateArray}
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import spinal.lib.misc.{InterruptCtrl, Prescaler, Timer}
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import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
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import vexriscv.plugin._
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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import spinal.lib.com.spi.ddr._
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import spinal.lib.bus.simple._
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import scala.collection.mutable.ArrayBuffer
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import scala.collection.Seq
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/**
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* Created by PIC32F_USER on 28/07/2017.
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*
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* Murax is a very light SoC which could work without any external component.
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* - ICE40-hx8k + icestorm => 53 Mhz, 2142 LC
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* - 0.37 DMIPS/Mhz
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* - 8 kB of on-chip ram
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* - JTAG debugger (eclipse/GDB/openocd ready)
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* - Interrupt support
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* - APB bus for peripherals
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* - 32 GPIO pin
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* - one 16 bits prescaler, two 16 bits timers
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* - one UART with tx/rx fifo
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*/
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case class MuraxConfig(coreFrequency : HertzNumber,
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onChipRamSize : BigInt,
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onChipRamHexFile : String,
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pipelineDBus : Boolean,
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pipelineMainBus : Boolean,
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pipelineApbBridge : Boolean,
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gpioWidth : Int,
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uartCtrlConfig : UartCtrlMemoryMappedConfig,
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xipConfig : SpiXdrMasterCtrl.MemoryMappingParameters,
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hardwareBreakpointCount : Int,
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cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){
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require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
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val genXip = xipConfig != null
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}
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object MuraxConfig{
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def default : MuraxConfig = default(false, false)
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def default(withXip : Boolean = false, bigEndian : Boolean = false) = MuraxConfig(
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coreFrequency = 12 MHz,
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onChipRamSize = 128 kB,
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onChipRamHexFile = null,
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pipelineDBus = true,
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pipelineMainBus = false,
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pipelineApbBridge = true,
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gpioWidth = 32,
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xipConfig = ifGen(withXip) (SpiXdrMasterCtrl.MemoryMappingParameters(
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SpiXdrMasterCtrl.Parameters(8, 12, SpiXdrParameter(2, 2, 1)).addFullDuplex(0,1,false),
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cmdFifoDepth = 32,
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rspFifoDepth = 32,
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xip = SpiXdrMasterCtrl.XipBusParameters(addressWidth = 24, lengthWidth = 2)
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)),
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hardwareBreakpointCount = if(withXip) 3 else 0,
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cpuPlugins = ArrayBuffer( //DebugPlugin added by the toplevel
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new IBusSimplePlugin(
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resetVector = if(withXip) 0xF001E000l else 0x00000000l,
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cmdForkOnSecondStage = true,
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cmdForkPersistence = withXip, //Required by the Xip controller
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prediction = NONE,
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catchAccessFault = false,
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compressedGen = false,
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bigEndian = bigEndian
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false,
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earlyInjection = false,
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bigEndian = bigEndian
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),
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new CsrPlugin(CsrPluginConfig.smallest(mtvecInit = if(withXip) 0xE0040020l else 0x00000020l)),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = false
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false
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),
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new YamlPlugin("cpu0.yaml")
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),
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uartCtrlConfig = UartCtrlMemoryMappedConfig(
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uartCtrlConfig = UartCtrlGenerics(
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dataWidthMax = 8,
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clockDividerWidth = 20,
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preSamplingSize = 1,
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samplingSize = 3,
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postSamplingSize = 1
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),
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initConfig = UartCtrlInitConfig(
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baudrate = 115200,
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dataLength = 7, //7 => 8 bits
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parity = UartParityType.NONE,
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stop = UartStopType.ONE
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),
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busCanWriteClockDividerConfig = false,
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busCanWriteFrameConfig = false,
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txFifoDepth = 16,
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rxFifoDepth = 16
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)
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)
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def fast = {
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val config = default
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//Replace HazardSimplePlugin to get datapath bypass
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config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[HazardSimplePlugin])) = new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true
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)
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// config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[LightShifterPlugin])) = new FullBarrelShifterPlugin()
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config
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}
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}
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case class Murax(config : MuraxConfig) extends Component{
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import config._
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val io = new Bundle {
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//Clocks / reset
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val asyncReset = in Bool()
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val mainClk = in Bool()
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//Main components IO
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val jtag = slave(Jtag())
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//Peripherals IO
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val gpioA = master(TriStateArray(gpioWidth bits))
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val uart = master(Uart())
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val xip = ifGen(genXip)(master(SpiXdrMaster(xipConfig.ctrl.spi)))
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}
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val resetCtrlClockDomain = ClockDomain(
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clock = io.mainClk,
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config = ClockDomainConfig(
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resetKind = BOOT
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)
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)
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val resetCtrl = new ClockingArea(resetCtrlClockDomain) {
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val mainClkResetUnbuffered = False
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//Implement an counter to keep the reset axiResetOrder high 64 cycles
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// Also this counter will automatically do a reset when the system boot.
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val systemClkResetCounter = Reg(UInt(6 bits)) init(0)
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when(systemClkResetCounter =/= U(systemClkResetCounter.range -> true)){
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systemClkResetCounter := systemClkResetCounter + 1
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mainClkResetUnbuffered := True
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}
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when(BufferCC(io.asyncReset)){
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systemClkResetCounter := 0
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}
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//Create all reset used later in the design
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val mainClkReset = RegNext(mainClkResetUnbuffered)
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val systemReset = RegNext(mainClkResetUnbuffered)
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}
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val systemClockDomain = ClockDomain(
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clock = io.mainClk,
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reset = resetCtrl.systemReset,
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frequency = FixedFrequency(coreFrequency)
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)
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val debugClockDomain = ClockDomain(
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|
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clock = io.mainClk,
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reset = resetCtrl.mainClkReset,
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frequency = FixedFrequency(coreFrequency)
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|
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)
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|
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|
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val system = new ClockingArea(systemClockDomain) {
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|
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val pipelinedMemoryBusConfig = PipelinedMemoryBusConfig(
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|
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addressWidth = 32,
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dataWidth = 32
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|
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)
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|
||||||
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|
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val bigEndianDBus = config.cpuPlugins.exists(_ match{ case plugin : DBusSimplePlugin => plugin.bigEndian case _ => false})
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|
||||||
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|
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//Arbiter of the cpu dBus/iBus to drive the mainBus
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|
||||||
//Priority to dBus, !! cmd transactions can change on the fly !!
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|
||||||
val mainBusArbiter = new MuraxMasterArbiter(pipelinedMemoryBusConfig, bigEndianDBus)
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|
||||||
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|
||||||
//Instanciate the CPU
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|
||||||
val cpu = new VexRiscv(
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|
||||||
config = VexRiscvConfig(
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|
||||||
plugins = cpuPlugins += new DebugPlugin(debugClockDomain, hardwareBreakpointCount)
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|
||||||
)
|
|
||||||
)
|
|
||||||
|
|
||||||
//Checkout plugins used to instanciate the CPU to connect them to the SoC
|
|
||||||
val timerInterrupt = False
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|
||||||
val externalInterrupt = False
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|
||||||
for(plugin <- cpu.plugins) plugin match{
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|
||||||
case plugin : IBusSimplePlugin =>
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|
||||||
mainBusArbiter.io.iBus.cmd <> plugin.iBus.cmd
|
|
||||||
mainBusArbiter.io.iBus.rsp <> plugin.iBus.rsp
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|
||||||
case plugin : DBusSimplePlugin => {
|
|
||||||
if(!pipelineDBus)
|
|
||||||
mainBusArbiter.io.dBus <> plugin.dBus
|
|
||||||
else {
|
|
||||||
mainBusArbiter.io.dBus.cmd << plugin.dBus.cmd.halfPipe()
|
|
||||||
mainBusArbiter.io.dBus.rsp <> plugin.dBus.rsp
|
|
||||||
}
|
|
||||||
}
|
|
||||||
case plugin : CsrPlugin => {
|
|
||||||
plugin.externalInterrupt := externalInterrupt
|
|
||||||
plugin.timerInterrupt := timerInterrupt
|
|
||||||
}
|
|
||||||
case plugin : DebugPlugin => plugin.debugClockDomain{
|
|
||||||
resetCtrl.systemReset setWhen(RegNext(plugin.io.resetOut))
|
|
||||||
io.jtag <> plugin.io.bus.fromJtag()
|
|
||||||
}
|
|
||||||
case _ =>
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//****** MainBus slaves ********
|
|
||||||
val mainBusMapping = ArrayBuffer[(PipelinedMemoryBus,SizeMapping)]()
|
|
||||||
val ram = new MuraxPipelinedMemoryBusRam(
|
|
||||||
onChipRamSize = onChipRamSize,
|
|
||||||
onChipRamHexFile = onChipRamHexFile,
|
|
||||||
pipelinedMemoryBusConfig = pipelinedMemoryBusConfig,
|
|
||||||
bigEndian = bigEndianDBus
|
|
||||||
)
|
|
||||||
mainBusMapping += ram.io.bus -> (0x00000000l, onChipRamSize)
|
|
||||||
|
|
||||||
val apbBridge = new PipelinedMemoryBusToApbBridge(
|
|
||||||
apb3Config = Apb3Config(
|
|
||||||
addressWidth = 20,
|
|
||||||
dataWidth = 32
|
|
||||||
),
|
|
||||||
pipelineBridge = pipelineApbBridge,
|
|
||||||
pipelinedMemoryBusConfig = pipelinedMemoryBusConfig
|
|
||||||
)
|
|
||||||
mainBusMapping += apbBridge.io.pipelinedMemoryBus -> (0xF0000000l, 1 MB)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//******** APB peripherals *********
|
|
||||||
val apbMapping = ArrayBuffer[(Apb3, SizeMapping)]()
|
|
||||||
val gpioACtrl = Apb3Gpio(gpioWidth = gpioWidth, withReadSync = true)
|
|
||||||
io.gpioA <> gpioACtrl.io.gpio
|
|
||||||
apbMapping += gpioACtrl.io.apb -> (0x00000, 4 kB)
|
|
||||||
|
|
||||||
val uartCtrl = Apb3UartCtrl(uartCtrlConfig)
|
|
||||||
uartCtrl.io.uart <> io.uart
|
|
||||||
externalInterrupt setWhen(uartCtrl.io.interrupt)
|
|
||||||
apbMapping += uartCtrl.io.apb -> (0x10000, 4 kB)
|
|
||||||
|
|
||||||
val timer = new MuraxApb3Timer()
|
|
||||||
timerInterrupt setWhen(timer.io.interrupt)
|
|
||||||
apbMapping += timer.io.apb -> (0x20000, 4 kB)
|
|
||||||
|
|
||||||
val xip = ifGen(genXip)(new Area{
|
|
||||||
val ctrl = Apb3SpiXdrMasterCtrl(xipConfig)
|
|
||||||
ctrl.io.spi <> io.xip
|
|
||||||
externalInterrupt setWhen(ctrl.io.interrupt)
|
|
||||||
apbMapping += ctrl.io.apb -> (0x1F000, 4 kB)
|
|
||||||
|
|
||||||
val accessBus = new PipelinedMemoryBus(PipelinedMemoryBusConfig(24,32))
|
|
||||||
mainBusMapping += accessBus -> (0xE0000000l, 16 MB)
|
|
||||||
|
|
||||||
ctrl.io.xip.fromPipelinedMemoryBus() << accessBus
|
|
||||||
val bootloader = Apb3Rom("src/main/c/murax/xipBootloader/crt.bin")
|
|
||||||
apbMapping += bootloader.io.apb -> (0x1E000, 4 kB)
|
|
||||||
})
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//******** Memory mappings *********
|
|
||||||
val apbDecoder = Apb3Decoder(
|
|
||||||
master = apbBridge.io.apb,
|
|
||||||
slaves = apbMapping.toSeq
|
|
||||||
)
|
|
||||||
|
|
||||||
val mainBusDecoder = new Area {
|
|
||||||
val logic = new MuraxPipelinedMemoryBusDecoder(
|
|
||||||
master = mainBusArbiter.io.masterBus,
|
|
||||||
specification = mainBusMapping.toSeq,
|
|
||||||
pipelineMaster = pipelineMainBus
|
|
||||||
)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
object Murax{
|
|
||||||
def main(args: Array[String]) {
|
|
||||||
SpinalVerilog(Murax(MuraxConfig.default))
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
object MuraxCfu{
|
|
||||||
def main(args: Array[String]) {
|
|
||||||
SpinalVerilog{
|
|
||||||
val config = MuraxConfig.default
|
|
||||||
config.cpuPlugins += new CfuPlugin(
|
|
||||||
stageCount = 1,
|
|
||||||
allowZeroLatency = true,
|
|
||||||
encodings = List(
|
|
||||||
CfuPluginEncoding (
|
|
||||||
instruction = M"-------------------------0001011",
|
|
||||||
functionId = List(14 downto 12),
|
|
||||||
input2Kind = CfuPlugin.Input2Kind.RS
|
|
||||||
)
|
|
||||||
),
|
|
||||||
busParameter = CfuBusParameter(
|
|
||||||
CFU_VERSION = 0,
|
|
||||||
CFU_INTERFACE_ID_W = 0,
|
|
||||||
CFU_FUNCTION_ID_W = 3,
|
|
||||||
CFU_REORDER_ID_W = 0,
|
|
||||||
CFU_REQ_RESP_ID_W = 0,
|
|
||||||
CFU_INPUTS = 2,
|
|
||||||
CFU_INPUT_DATA_W = 32,
|
|
||||||
CFU_OUTPUTS = 1,
|
|
||||||
CFU_OUTPUT_DATA_W = 32,
|
|
||||||
CFU_FLOW_REQ_READY_ALWAYS = false,
|
|
||||||
CFU_FLOW_RESP_READY_ALWAYS = false,
|
|
||||||
CFU_WITH_STATUS = true,
|
|
||||||
CFU_RAW_INSN_W = 32,
|
|
||||||
CFU_CFU_ID_W = 4,
|
|
||||||
CFU_STATE_INDEX_NUM = 5
|
|
||||||
)
|
|
||||||
)
|
|
||||||
|
|
||||||
val toplevel = Murax(config)
|
|
||||||
|
|
||||||
toplevel.rework {
|
|
||||||
for (plugin <- toplevel.system.cpu.plugins) plugin match {
|
|
||||||
case plugin: CfuPlugin => plugin.bus.toIo().setName("miaou")
|
|
||||||
case _ =>
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
toplevel
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
object Murax_iCE40_hx8k_breakout_board_xip{
|
|
||||||
|
|
||||||
case class SB_GB() extends BlackBox{
|
|
||||||
val USER_SIGNAL_TO_GLOBAL_BUFFER = in Bool()
|
|
||||||
val GLOBAL_BUFFER_OUTPUT = out Bool()
|
|
||||||
}
|
|
||||||
|
|
||||||
case class SB_IO_SCLK() extends BlackBox{
|
|
||||||
addGeneric("PIN_TYPE", B"010000")
|
|
||||||
val PACKAGE_PIN = out Bool()
|
|
||||||
val OUTPUT_CLK = in Bool()
|
|
||||||
val CLOCK_ENABLE = in Bool()
|
|
||||||
val D_OUT_0 = in Bool()
|
|
||||||
val D_OUT_1 = in Bool()
|
|
||||||
setDefinitionName("SB_IO")
|
|
||||||
}
|
|
||||||
|
|
||||||
case class SB_IO_DATA() extends BlackBox{
|
|
||||||
addGeneric("PIN_TYPE", B"110000")
|
|
||||||
val PACKAGE_PIN = inout(Analog(Bool))
|
|
||||||
val CLOCK_ENABLE = in Bool()
|
|
||||||
val INPUT_CLK = in Bool()
|
|
||||||
val OUTPUT_CLK = in Bool()
|
|
||||||
val OUTPUT_ENABLE = in Bool()
|
|
||||||
val D_OUT_0 = in Bool()
|
|
||||||
val D_OUT_1 = in Bool()
|
|
||||||
val D_IN_0 = out Bool()
|
|
||||||
val D_IN_1 = out Bool()
|
|
||||||
setDefinitionName("SB_IO")
|
|
||||||
}
|
|
||||||
|
|
||||||
case class Murax_iCE40_hx8k_breakout_board_xip() extends Component{
|
|
||||||
val io = new Bundle {
|
|
||||||
val mainClk = in Bool()
|
|
||||||
val jtag_tck = in Bool()
|
|
||||||
val jtag_tdi = in Bool()
|
|
||||||
val jtag_tdo = out Bool()
|
|
||||||
val jtag_tms = in Bool()
|
|
||||||
val uart_txd = out Bool()
|
|
||||||
val uart_rxd = in Bool()
|
|
||||||
|
|
||||||
val mosi = inout(Analog(Bool))
|
|
||||||
val miso = inout(Analog(Bool))
|
|
||||||
val sclk = out Bool()
|
|
||||||
val spis = out Bool()
|
|
||||||
|
|
||||||
val led = out Bits(8 bits)
|
|
||||||
}
|
|
||||||
val murax = Murax(MuraxConfig.default(withXip = true).copy(onChipRamSize = 8 kB))
|
|
||||||
murax.io.asyncReset := False
|
|
||||||
|
|
||||||
val mainClkBuffer = SB_GB()
|
|
||||||
mainClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.mainClk
|
|
||||||
mainClkBuffer.GLOBAL_BUFFER_OUTPUT <> murax.io.mainClk
|
|
||||||
|
|
||||||
val jtagClkBuffer = SB_GB()
|
|
||||||
jtagClkBuffer.USER_SIGNAL_TO_GLOBAL_BUFFER <> io.jtag_tck
|
|
||||||
jtagClkBuffer.GLOBAL_BUFFER_OUTPUT <> murax.io.jtag.tck
|
|
||||||
|
|
||||||
io.led <> murax.io.gpioA.write(7 downto 0)
|
|
||||||
|
|
||||||
murax.io.jtag.tdi <> io.jtag_tdi
|
|
||||||
murax.io.jtag.tdo <> io.jtag_tdo
|
|
||||||
murax.io.jtag.tms <> io.jtag_tms
|
|
||||||
murax.io.gpioA.read <> 0
|
|
||||||
murax.io.uart.txd <> io.uart_txd
|
|
||||||
murax.io.uart.rxd <> io.uart_rxd
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
val xip = new ClockingArea(murax.systemClockDomain) {
|
|
||||||
RegNext(murax.io.xip.ss.asBool) <> io.spis
|
|
||||||
|
|
||||||
val sclkIo = SB_IO_SCLK()
|
|
||||||
sclkIo.PACKAGE_PIN <> io.sclk
|
|
||||||
sclkIo.CLOCK_ENABLE := True
|
|
||||||
|
|
||||||
sclkIo.OUTPUT_CLK := ClockDomain.current.readClockWire
|
|
||||||
sclkIo.D_OUT_0 <> murax.io.xip.sclk.write(0)
|
|
||||||
sclkIo.D_OUT_1 <> RegNext(murax.io.xip.sclk.write(1))
|
|
||||||
|
|
||||||
val datas = for ((data, pin) <- (murax.io.xip.data, List(io.mosi, io.miso)).zipped) yield new Area {
|
|
||||||
val dataIo = SB_IO_DATA()
|
|
||||||
dataIo.PACKAGE_PIN := pin
|
|
||||||
dataIo.CLOCK_ENABLE := True
|
|
||||||
|
|
||||||
dataIo.OUTPUT_CLK := ClockDomain.current.readClockWire
|
|
||||||
dataIo.OUTPUT_ENABLE <> data.writeEnable
|
|
||||||
dataIo.D_OUT_0 <> data.write(0)
|
|
||||||
dataIo.D_OUT_1 <> RegNext(data.write(1))
|
|
||||||
|
|
||||||
dataIo.INPUT_CLK := ClockDomain.current.readClockWire
|
|
||||||
data.read(0) := dataIo.D_IN_0
|
|
||||||
data.read(1) := RegNext(dataIo.D_IN_1)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
def main(args: Array[String]) {
|
|
||||||
SpinalVerilog(Murax_iCE40_hx8k_breakout_board_xip())
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
object MuraxDhrystoneReady{
|
|
||||||
def main(args: Array[String]) {
|
|
||||||
SpinalVerilog(Murax(MuraxConfig.fast.copy(onChipRamSize = 256 kB)))
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
object MuraxDhrystoneReadyMulDivStatic{
|
|
||||||
def main(args: Array[String]) {
|
|
||||||
SpinalVerilog({
|
|
||||||
val config = MuraxConfig.fast.copy(onChipRamSize = 256 kB)
|
|
||||||
config.cpuPlugins += new MulPlugin
|
|
||||||
config.cpuPlugins += new DivPlugin
|
|
||||||
config.cpuPlugins.remove(config.cpuPlugins.indexWhere(_.isInstanceOf[BranchPlugin]))
|
|
||||||
config.cpuPlugins +=new BranchPlugin(
|
|
||||||
earlyBranch = false,
|
|
||||||
catchAddressMisaligned = false
|
|
||||||
)
|
|
||||||
config.cpuPlugins += new IBusSimplePlugin(
|
|
||||||
resetVector = 0x00000000l,
|
|
||||||
cmdForkOnSecondStage = true,
|
|
||||||
cmdForkPersistence = false,
|
|
||||||
prediction = STATIC,
|
|
||||||
catchAccessFault = false,
|
|
||||||
compressedGen = false
|
|
||||||
)
|
|
||||||
config.cpuPlugins.remove(config.cpuPlugins.indexWhere(_.isInstanceOf[LightShifterPlugin]))
|
|
||||||
config.cpuPlugins += new FullBarrelShifterPlugin
|
|
||||||
Murax(config)
|
|
||||||
})
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
//Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
|
|
||||||
object MuraxWithRamInit{
|
|
||||||
def main(args: Array[String]) {
|
|
||||||
SpinalVerilog(Murax(MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")))
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
object Murax_arty{
|
|
||||||
def main(args: Array[String]) {
|
|
||||||
val hex = "src/main/c/murax/hello_world/build/hello_world.hex"
|
|
||||||
SpinalVerilog(Murax(MuraxConfig.default(false).copy(coreFrequency = 100 MHz,onChipRamSize = 32 kB, onChipRamHexFile = hex)))
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
object MuraxAsicBlackBox extends App{
|
|
||||||
println("Warning this soc do not has any rom to boot on.")
|
|
||||||
val config = SpinalConfig()
|
|
||||||
config.addStandardMemBlackboxing(blackboxAll)
|
|
||||||
config.generateVerilog(Murax(MuraxConfig.default()))
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,42 +0,0 @@
|
||||||
.text
|
|
||||||
.global _start
|
|
||||||
.type _start, @function
|
|
||||||
|
|
||||||
_start:
|
|
||||||
# Initialize global pointer
|
|
||||||
.option push
|
|
||||||
.option norelax
|
|
||||||
la gp, __global_pointer$
|
|
||||||
.option pop
|
|
||||||
|
|
||||||
li sp, 0x1fff0
|
|
||||||
|
|
||||||
# Clear the bss segment
|
|
||||||
la a0, __bss_start
|
|
||||||
la a1, __BSS_END__
|
|
||||||
|
|
||||||
clear_bss:
|
|
||||||
bgeu a0, a1, finish_bss
|
|
||||||
sb x0, 0(a0)
|
|
||||||
addi a0, a0, 1
|
|
||||||
beq x0, x0, clear_bss
|
|
||||||
finish_bss:
|
|
||||||
|
|
||||||
nop //!
|
|
||||||
|
|
||||||
call main
|
|
||||||
|
|
||||||
nop //!
|
|
||||||
|
|
||||||
# abort execution here
|
|
||||||
ebreak
|
|
||||||
|
|
||||||
.section .rodata
|
|
||||||
alfabet:
|
|
||||||
.string "abcdefghijklmnopqrstuwxyz"
|
|
||||||
slowo:
|
|
||||||
|
|
||||||
.section .data
|
|
||||||
wynik:
|
|
||||||
.string "mpabi"
|
|
||||||
.space 26 # rezerwuje 26 bajtów dla wyniku, zainicjowane na 0
|
|
||||||
|
|
@ -1,39 +0,0 @@
|
||||||
.text
|
|
||||||
.global _start
|
|
||||||
.type _start, @function
|
|
||||||
|
|
||||||
_start:
|
|
||||||
# Initialize global pointer
|
|
||||||
.option push
|
|
||||||
.option norelax
|
|
||||||
la gp, __global_pointer$
|
|
||||||
.option pop
|
|
||||||
|
|
||||||
# Initialize stack pointer from linker script symbol
|
|
||||||
la sp, __stack_top
|
|
||||||
|
|
||||||
# Clear the BSS segment
|
|
||||||
la a0, __bss_start
|
|
||||||
la a1, __bss_end
|
|
||||||
|
|
||||||
clear_bss:
|
|
||||||
bgeu a0, a1, finish_bss
|
|
||||||
sb x0, 0(a0)
|
|
||||||
addi a0, a0, 1
|
|
||||||
j clear_bss
|
|
||||||
finish_bss:
|
|
||||||
|
|
||||||
call main
|
|
||||||
|
|
||||||
ebreak
|
|
||||||
|
|
||||||
.section .rodata
|
|
||||||
|
|
||||||
alfabet:
|
|
||||||
.string "abcdefghijklmnopqrstuwxyz"
|
|
||||||
slowo:
|
|
||||||
|
|
||||||
.section .data
|
|
||||||
wynik:
|
|
||||||
.string "mpabi"
|
|
||||||
.space 26 # rezerwuje 26 bajtów dla wyniku, zainicjowane na 0
|
|
||||||
|
|
@ -41,15 +41,7 @@ struct model {
|
||||||
uint32_t len ;
|
uint32_t len ;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
//alg
|
|
||||||
// prosta implementacji func. z bibl. std. strok przy uzyciu gpt3.5
|
|
||||||
//
|
|
||||||
|
|
||||||
#define NULL ((void*) 0)
|
#define NULL ((void*) 0)
|
||||||
|
|
||||||
//
|
|
||||||
// Funkcja pomocnicza do sprawdzania, czy znak jest wśród delimiterów
|
|
||||||
bool is_delim(char c, const char *delims) {
|
bool is_delim(char c, const char *delims) {
|
||||||
while (*delims) {
|
while (*delims) {
|
||||||
if (c == *delims) {
|
if (c == *delims) {
|
||||||
|
|
@ -60,101 +52,65 @@ bool is_delim(char c, const char *delims) {
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Najprostsza implementacja funkcji strtok
|
|
||||||
char *simple_strtok(char *str, const char *delims) {
|
char *simple_strtok(char *str, const char *delims) {
|
||||||
char *static_str = (char *) NULL; // Przechowuje wskaźnik do bieżącej pozycji w ciągu
|
static char *static_str =(char *) NULL; // Stores the position in the string
|
||||||
|
|
||||||
// Jeśli przekazano nowy ciąg, zaktualizuj static_str
|
if (str !=(char *) NULL) {
|
||||||
if (str == NULL) {
|
static_str = str;
|
||||||
return (char *) NULL; // str nie wskazuje na zdanie !!!
|
|
||||||
}
|
}
|
||||||
static_str = str;
|
|
||||||
|
|
||||||
// " .,mpabi"
|
if (static_str == (char *) NULL) {
|
||||||
// ^
|
return (char *)NULL;
|
||||||
// Pomiń początkowe delimitery
|
}
|
||||||
|
|
||||||
|
// Skip initial delimiters
|
||||||
while (*static_str && is_delim(*static_str, delims)) {
|
while (*static_str && is_delim(*static_str, delims)) {
|
||||||
static_str++;
|
static_str++;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Jeśli doszliśmy do końca ciągu, zwróć NULL
|
|
||||||
if (*static_str == '\0') {
|
if (*static_str == '\0') {
|
||||||
return (char *) NULL;
|
return (char *)NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Zapisz początek tokenu
|
|
||||||
char *token_start = static_str;
|
char *token_start = static_str;
|
||||||
|
|
||||||
|
// Find the end of the token
|
||||||
//,. mpabi pabi
|
|
||||||
// Znajdź koniec tokenu
|
|
||||||
while (*static_str && !is_delim(*static_str, delims)) {
|
while (*static_str && !is_delim(*static_str, delims)) {
|
||||||
static_str++;
|
static_str++;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Jeśli znaleziono delimitery, zamień je na '\0' i zaktualizuj static_str
|
|
||||||
if (*static_str) {
|
if (*static_str) {
|
||||||
*static_str = '\0';
|
*static_str = '\0';
|
||||||
static_str++;
|
static_str++;
|
||||||
|
} else {
|
||||||
|
static_str = (char *)NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Zwróć początek tokenu
|
|
||||||
return token_start;
|
return token_start;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
char buf[1000];
|
char buf[1000];
|
||||||
struct model * p = (struct model *) buf; //p[1]
|
struct model * p = (struct model *) buf; //p[1]
|
||||||
//
|
|
||||||
|
|
||||||
|
|
||||||
////func alg
|
int alg(char *ptr) {
|
||||||
//in: ptr to date
|
const char *delims = " ,.!?:;\n\t";
|
||||||
//return: count of words
|
|
||||||
int alg (char * ptr) {
|
|
||||||
|
|
||||||
const char *delims = " ,.!?:;\n\t";
|
|
||||||
|
|
||||||
int pos = 0;
|
int pos = 0;
|
||||||
|
|
||||||
while (char *token = simple_strtok(ptr, delims)) {
|
char *token = simple_strtok(ptr, delims);
|
||||||
|
while (token != (char *)NULL) {
|
||||||
p[pos].ptr = token;
|
p[pos].ptr = token;
|
||||||
//p[pos].len = strlen(token);
|
p[pos].len = strlen(token);
|
||||||
p[pos].len = pos;
|
++pos;
|
||||||
|
token = simple_strtok((char *)NULL, delims); // Set ptr to NULL after the first call to continue tokenizing the same string
|
||||||
token = token + strlen(token) + 1;
|
|
||||||
++pos;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return pos;
|
return pos;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
|
||||||
struct model {
|
|
||||||
char * str;
|
|
||||||
uint32_t len ;
|
|
||||||
} tab [10] ;
|
|
||||||
*/
|
|
||||||
|
|
||||||
int main() {
|
int main() {
|
||||||
// Seccess is often
|
|
||||||
// ^
|
|
||||||
char *str = " Success is often defined as the ability to reach your goals in life, whatever those goals may be. In some ways, a better word for success might be attainment, accomplishment, or progress. It is not necessarily a destination but a journey that helps develop the skills and resources you need to thrive.";
|
char *str = " Success is often defined as the ability to reach your goals in life, whatever those goals may be. In some ways, a better word for success might be attainment, accomplishment, or progress. It is not necessarily a destination but a journey that helps develop the skills and resources you need to thrive.";
|
||||||
|
alg(str);
|
||||||
/*
|
|
||||||
struct model *ptr = (struct model *) alloc(LEN);
|
|
||||||
if (ptr != (struct model *)NULL) {
|
|
||||||
ptr->str = alloc(strlen((char *)str) + 1);
|
|
||||||
if (ptr->str != (char *)NULL) {
|
|
||||||
strcpy (ptr->str, (char *)str);
|
|
||||||
ptr->len = strlen(ptr->str);
|
|
||||||
|
|
||||||
int8_t count = alg(ptr->str);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
*/
|
|
||||||
int w = alg(str);
|
|
||||||
asm ("nop");
|
asm ("nop");
|
||||||
|
|
||||||
return 1;
|
return 1;
|
||||||
|
|
|
||||||
|
|
@ -1,43 +0,0 @@
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
RAM (wx) : ORIGIN = 0x0, LENGTH = 128K
|
|
||||||
}
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
*(.text*)
|
|
||||||
*(.rodata*)
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data*)
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
/* Add stack at the end of RAM */
|
|
||||||
. = ALIGN(4);
|
|
||||||
_end = .;
|
|
||||||
PROVIDE(end = .);
|
|
||||||
|
|
||||||
/* Define stack size and location */
|
|
||||||
_stack_size = 0x4000; /* Example stack size: 16KB */
|
|
||||||
_stack_end = ORIGIN(RAM) + LENGTH(RAM); /* End of RAM */
|
|
||||||
_stack_start = _stack_end - _stack_size; /* Calculate start of the stack */
|
|
||||||
.stack (NOLOAD) :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
. = . + _stack_size;
|
|
||||||
. = ALIGN(4);
|
|
||||||
_sp = .;
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
PROVIDE(__stack = _sp);
|
|
||||||
}
|
|
||||||
|
|
@ -1,67 +0,0 @@
|
||||||
/* Linker script for a system with 128KB RAM starting at 0x10000 */
|
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
RAM (wx) : ORIGIN = 0x0000, LENGTH = 128K
|
|
||||||
}
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* Place code and readonly data at the beginning of RAM */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
*(.text*)
|
|
||||||
*(.rodata*)
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
/* Place initialized data right after the .text section */
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
*(.data*)
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
/* Uninitialized data (BSS) follows initialized data */
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
. = ALIGN(4);
|
|
||||||
__bss_start = .;
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(4);
|
|
||||||
__bss_end = .;
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
/* Define heap start right after bss */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__heap_start = .;
|
|
||||||
PROVIDE(heap_start = __heap_start);
|
|
||||||
|
|
||||||
/* Leave space for the heap by not explicitly defining its end */
|
|
||||||
/* The heap grows towards the stack */
|
|
||||||
|
|
||||||
/* Reserve space for the stack at the end of RAM */
|
|
||||||
/* Let's say we want a 16KB stack */
|
|
||||||
. = ALIGN(4);
|
|
||||||
__stack_size = 16K; /* Size of the stack */
|
|
||||||
__stack_top = ORIGIN(RAM) + LENGTH(RAM); /* Top of the stack */
|
|
||||||
__stack_start = __stack_top - __stack_size; /* Start of the stack */
|
|
||||||
.stack (NOLOAD) :
|
|
||||||
{
|
|
||||||
. = __stack_start;
|
|
||||||
. += __stack_size; /* Allocate space for the stack */
|
|
||||||
. = ALIGN(4);
|
|
||||||
} > RAM
|
|
||||||
|
|
||||||
PROVIDE(__stack = __stack_top);
|
|
||||||
PROVIDE(stack_top = __stack_top);
|
|
||||||
PROVIDE(stack_start = __stack_start);
|
|
||||||
|
|
||||||
/* Heap end is dynamically located at the start of the stack */
|
|
||||||
__heap_end = __stack_start;
|
|
||||||
PROVIDE(heap_end = __heap_end);
|
|
||||||
|
|
||||||
/* End of RAM usage */
|
|
||||||
. = ALIGN(4);
|
|
||||||
_end = .;
|
|
||||||
PROVIDE(end = _end);
|
|
||||||
}
|
|
||||||
|
|
@ -1,13 +0,0 @@
|
||||||
MEMORY
|
|
||||||
{
|
|
||||||
RAM (wx) : ORIGIN = 0x10000, LENGTH = 128K
|
|
||||||
}
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
.text : { *(.text*) } > RAM
|
|
||||||
.rodata : { *(.rodata*) } > RAM
|
|
||||||
.data : { *(.data*) } > RAM
|
|
||||||
.bss : { *(.bss*) } > RAM
|
|
||||||
_end = .; /* Definiuje koniec sekcji danych, może być używane do określenia rozmiaru sterty */
|
|
||||||
}
|
|
||||||
Loading…
Reference in New Issue